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10 MHz, 20 V/s, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier
AD8253
FEATURES
Small package: 10-lead MSOP Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting Wide supply: 5 V to 15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 Low gain drift: 10 ppm/C (maximum) Low offset drift: 1.2 V/C (maximum), G = 1000 Excellent ac performance Fast settling time: 780 ns to 0.001% (maximum) High slew rate: 20 V/s (minimum) Low distortion: -110 dB THD at 1 kHz,10 V swing High CMRR over frequency: 100 dB to 20 kHz (minimum) Low noise: 10 nV/Hz, G = 1000 (maximum) Low power: 4 mA
FUNCTIONAL BLOCK DIAGRAM
DGND WR
2 6
A1
5
A0
4
-IN 1
LOGIC
7
OUT
+IN 10
AD8253
8 3 9
+VS
-VS
REF
Figure 1.
80 70 60 50 G = 1000
APPLICATIONS
Data acquisition Biomedical analysis Test and measurement
GAIN (dB)
40 30 20 10 0 -10
G = 100
GENERAL DESCRIPTION
The AD8253 is an instrumentation amplifier with digitally programmable gains that has gigaohm (G) input impedance, low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-todigital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of -110 dB, and fast settling time of 780 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.2 V/C and 10 ppm/C, respectively, for G = 1000. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 100 dB at G = 1000 from dc to 20 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8253 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. The AD8253 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see Figure 1 for the functional block diagram). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use transparent gain mode, where the state of logic levels at the gain port determines the gain.
G = 10
G=1
10k
100k 1M FREQUENCY (Hz)
10M
100M
Figure 2. Gain vs. Frequency
Table 1. Instrumentation Amplifiers by Category
General Purpose AD82201 AD8221 AD8222 AD82241 AD8228
1
Zero Drift AD82311 AD85531 AD85551 AD85561 AD85571
Mil Grade AD620 AD621 AD524 AD526 AD624
Low Power AD6271 AD6231 AD82231
High Speed PGA AD8250 AD8251 AD8253
Rail-to-rail output.
The AD8253 is available in a 10-lead MSOP package and is specified over the -40C to +85C temperature range, making it an excellent solution for applications where size and packing density are important considerations.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
006983-023
-20 1k
06983-001
AD8253 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 16 Gain Selection ............................................................................. 16 Power Supply Regulation and Bypassing ................................ 18 Input Bias Current Return Path ............................................... 18 Input Protection ......................................................................... 18 Reference Terminal .................................................................... 19 Common-Mode Input Voltage Range ..................................... 19 Layout .......................................................................................... 19 RF Interference ........................................................................... 19 Driving an Analog-to-Digital Converter ................................ 20 Applications Information .............................................................. 21 Differential Output .................................................................... 21 Setting Gains with a Microcontroller ...................................... 21 Data Acquisition ......................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
7/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8253 SPECIFICATIONS
+VS = +15 V, -VS = -15 V, VREF = 0 V @ TA = 25C, G = 1, RL = 2 k, unless otherwise noted. Table 2.
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR to 20 kHz 1 G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz, RTI G=1 G = 10 G = 100 G = 1000 0.1 Hz to 10 Hz, RTI G=1 G = 10 G = 100 G = 1000 Current Noise, 1 kHz Current Noise, 0.1 Hz to 10 Hz VOLTAGE OFFSET Offset RTI VOS Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature 2 Average TC Input Offset Current Over Temperature Average TC DYNAMIC RESPONSE Small-Signal -3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Conditions +IN = -IN = -10 V to +10 V 80 96 100 100 +IN = -IN = -10 V to +10 V 80 96 100 100 dB dB dB dB 100 120 120 120 dB dB dB dB Min Typ Max Unit
45 12 11 10 2.5 1 0.5 0.5 5 60 G = 1, 10, 100, 1000 T = -40C to +85C T = -40C to +85C VS = 5 V to 15 V 5 T = -40C to +85C T = -40C to +85C T = -40C to +85C T = -40C to +85C 40 5 150 + 900/G 210 + 900/G 1.2 + 5/G 5 + 25/G 50 60 400 40 40 160
nV/Hz nV/Hz nV/Hz nV/Hz V p-p V p-p V p-p V p-p pA/Hz pA p-p V V V/C V/V nA nA pA/C nA nA pA/C
10 4 550 60 OUT = 10 V step 700 680 1.5 14
MHz MHz kHz kHz ns ns s s
Rev. 0 | Page 3 of 24
AD8253
Parameter Settling Time 0.001% G=1 G = 10 G =100 G = 1000 Slew Rate G=1 G = 10 G = 100 G = 1000 Total Harmonic Distortion + Noise Conditions OUT = 10 V step Min Typ Max 780 880 1.8 1.8 20 20 12 2 f = 1 kHz, RL = 10 k, 10 V, G = 1, 10 Hz to 22 kHz bandpass filter G = 1, 10, 100, 1000 OUT = 10 V 1 -110 Unit ns ns s s V/s V/s V/s V/s dB
GAIN Gain Range Gain Error G=1 G = 10, 100, 1000 Gain Nonlinearity G=1 G = 10 G = 100 G = 1000 Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range Over Temperature 3 OUTPUT Output Swing Over Temperature 4 Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output DIGITAL LOGIC Digital Ground Voltage, DGND Digital Input Voltage Low Digital Input Voltage High Digital Input Current Gain Switching Time 5 tSU tHD t WR -LOW t WR -HIGH
1000 0.03 0.04
V/V % % ppm ppm ppm ppm ppm/C
OUT = -10 V to +10 V RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 All gains
3
5 3 18 110 10
4||1.25 1||5 VS = 5 V to 15 V T = -40C to +85C -VS + 1 -VS + 1.2 -13.7 -13.7 37 20 +IN, -IN, REF = 0 -VS 1 0.0001 Referred to GND Referred to GND Referred to GND -VS + 4.25 DGND 1.5 0 +VS - 2.7 1.2 +VS 325 See Figure 3 timing diagram 15 30 20 15 1 +VS +VS - 1.5 +VS - 1.7 +13.6 +13.6
G||pF G||pF V V V V mA k A V V/V V V V A ns ns ns ns ns
T = -40C to +85C
1
Rev. 0 | Page 4 of 24
AD8253
Parameter POWER SUPPLY Operating Range Quiescent Current, +IS Quiescent Current, -IS Over Temperature TEMPERATURE RANGE Specified Performance
1 2
Conditions
Min 5
Typ
Max 15 5.3 5.3 6 +85
Unit V mA mA mA C
4.6 4.5 T = -40C to +85C -40
See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency. Input bias current over temperature: minimum at hot and maximum at cold. 3 See Figure 30 for input voltage limit vs. supply voltage and temperature. 4 See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads. 5 Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
tWR-HIGH
WR
tWR-LOW
tSU
A0, A1
tHD
06983-003
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
Rev. 0 | Page 5 of 24
AD8253 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Common-Mode Input Voltage Differential Input Voltage Digital Logic Inputs Storage Temperature Range Operating Temperature Range2 Lead Temperature (Soldering 10 sec) Junction Temperature JA (4-Layer JEDEC Standard Board) Package Glass Transition Temperature
1
Rating 17 V See Figure 4 Indefinite1 VS VS VS -65C to +125C -40C to +85C 300C 140C 112C/W 140C
power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some of which is dissipated in the load (VOUT x IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power - Load Power)
V V PD = (VS x I S ) + S x OUT 2 RL
VOUT 2 - RL
In single-supply operation with RL referenced to -VS, the worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board.
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -40
Assumes the load is referenced to midsupply. 2 Temperature for specified performance is -40C to +85C. For performance to +125C, see the Typical Performance Characteristics section.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8253 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8253. Exceeding a junction temperature of 140C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as
MAXIMUM POWER DISSIPATION (W)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
TJ = TA + (PD x JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent
Rev. 0 | Page 6 of 24
06983-004
AD8253 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
-IN 1 DGND 2 -VS 3 A1 5
10 +IN
AD8253
9
REF
6
WR
Figure 5. 10-Lead MSOP (RM-10) Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic -IN DGND -VS A0 A1 WR OUT +VS REF +IN Description Inverting Input Terminal. True differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable. Output Terminal. Positive Supply Terminal. Reference Voltage Terminal. Noninverting Input Terminal. True differential input.
Rev. 0 | Page 7 of 24
06983-005
8 +VS TOP VIEW A0 4 (Not to Scale) 7 OUT
AD8253 TYPICAL PERFORMANCE CHARACTERISTICS
TA @ 25C, +VS = +15 V, -VS = -15 V, RL = 10 k, unless otherwise noted.
210 240 180 210
NUMBER OF UNITS
NUMBER OF UNITS
150 120 90 60
180 150 120 90 60
30 0
30
06983-006
-60
-40
-20 CMRR (V/V)
0
20
-60
-40
-20
0
20
40
60
INPUT OFFSET CURRENT (nA)
Figure 6. Typical Distribution of CMRR, G = 1
Figure 9. Typical Distribution of Input Offset Current
180
90 80
150
NUMBER OF UNITS
70
NOISE (nV/Hz)
120
60 50 40 30 20 G = 10 G = 100 G=1
90
60
30
10
06983-010
-200
-100
0
100
200
06983-007
0
0
G = 1000 1 10 100 1k 10k 100k
INPUT OFFSET VOLTAGE, VOSI , RTI (V)
FREQUENCY (Hz)
Figure 7. Typical Distribution of Offset Voltage, VOSI
Figure 10. Voltage Spectral Density Noise vs. Frequency
300 250 200 150 100 50
2V/DIV 1s/DIV
NUMBER OF UNITS
-90
-60
-30
0
30
60
90
INPUT BIAS CURRENT (nA)
06983-008
0
Figure 8. Typical Distribution of Input Bias Current
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
Rev. 0 | Page 8 of 24
06983-011
06983-009
0
AD8253
20 CHANGE IN INPUT OFFSET VOLTAGE (V) 18 16 14 12 10 8 6 4 2 0.1 1 WARM-UP TIME (Minutes) 10
06983-015 06983-017 06983-016
500nV/DIV
1s/DIV
06983-012
0 0.01
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000
Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000
18 16 14
140 120 100 G = 1000 G = 100
NOISE (pA/Hz)
12
PSRR (dB)
10 8 6 4 2
06983-013
80 G=1 60 40 20 0 10 G = 10
0
1
10
100
1k
10k
100k
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Current Noise Spectral Density vs. Frequency
Figure 16. Positive PSRR vs. Frequency, RTI
140 120 100 G = 100 G = 1000
PSRR (dB)
80 G = 10 60 40 20 0 10
G=1
140pA/DIV
1s/DIV
06983-014
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. 0.1 Hz to 10 Hz Current Noise
Figure 17. Negative PSRR vs. Frequency, RTI
Rev. 0 | Page 9 of 24
AD8253
20 10 IB+ 12.0 10.5 9.0 IB- 7.5 6.0 4.5 3.0 1.5
06983-018
120
100
INPUT OFFSET CURRENT (nA)
INPUT BIAS CURRENT (nA)
0 -10 -20 -30 -40 -50 -60 -15
80
G = 1000
CMRR (dB)
G = 100 60 G = 10 40
IOS
20
G=1
-10
-5 0 5 COMMON-MODE VOLTAGE (V)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage
Figure 21. CMRR vs. Frequency, 1 k Source Imbalance
30 25
INPUT BIAS CURRENT AND OFFSET CURRENT (nA)
15
10
20
CMRR (V/V)
15 10 IB- 5 0 -5 IOS IB+
5
0
-5
-10
06983-019
-40
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
140
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (C)
Figure 19. Input Bias Current and Offset Current vs. Temperature
Figure 22. CMRR vs. Temperature, G = 1
120
G = 1000 G = 100
80 70
100
60 50
G = 1000
80
CMRR (dB) GAIN (dB)
G=1 60 G = 10 40
40 30 20 10 0 -10
G = 100
G = 10
G=1
20
100
1k
10k
100k
1M
06983-020
10k
FREQUENCY (Hz)
100k 1M FREQUENCY (Hz)
10M
100M
Figure 20. CMRR vs. Frequency
Figure 23. Gain vs. Frequency
Rev. 0 | Page 10 of 24
006983-023
0 10
-20 1k
06983-022
-10 -60
-15 -50
06983-021
0 15
0 10
AD8253
40 30 20 10 0 -10 -20 -30
06983-024
400 300
NONLINEARITY (10 ppm/DIV)
NONLINEARITY (10ppm/DIV)
200 100 0 -100 -200 -300
06983-027 06983-029
06983-028
-40 -10
-8
-6
-4
-2
0
2
4
6
8
10
-400 -10
-8
-6
-4
-2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity, G = 1, RL = 10 k, 2 k, 600
Figure 27. Gain Nonlinearity, G = 1000, RL = 10 k, 2 k, 600
40
INPUT COMMON-MODE VOLTAGE (V)
16 12 8 4 -4V, +1.9V 0 -4V, -1.9V -4 -8 -12 -16 -16 -14.1V, -7.3V
0V, +13.9V VS, 15V
30
NONLINEARITY (10ppm/DIV)
20 10 0 -10 -20 -30
06983-025
-14.1V, +7.3V
0V, +3.8V
+13.8V, +7.3V
+3.8V, +1.9V VS = 5V +3.8V, -1.9V
0V, -4.2V
+13.8V, -7.3V
-40 -10
0V, -14.2V -12 -8 -4 0 4 8 12 16 OUTPUT VOLTAGE (V)
-8
-6
-4
-2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity, G = 10, RL = 10 k, 2 k, 600
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1
80
INPUT COMMON-MODE VOLTAGE (V)
16 12 8 -14.4V, +6V 4 -4.3V, +2V 0 -4.3V, -2V -4 -14.4V, -6V -8 -12 -16 -16
0V, +13.7V VS 15V
60
NONLINEARITY (10ppm/DIV)
40 20 0 -20 -40 -60
06983-026
0V, +3.8V
+14.1V, +6V +4.3V, +2V
VS = 5V +4.3V, -2V 0V, -4.2V +14.1V, -6V
-80 -10
0V, -14.1V -12 -8 -4 0 4 8 12 16 OUTPUT VOLTAGE (V)
-8
-6
-4
-2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 26. Gain Nonlinearity, G = 100, RL = 10 k, 2 k, 600
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 1000
Rev. 0 | Page 11 of 24
AD8253
+VS -1 -2 +25C -40C +125C +85C
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
+VS -0.2 -0.4 -0.6 -0.8 -1.0 +85C +125C
INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES
+25C
-40C
+2 +1 +125C -VS 4 6 8
-40C
+25C
+1.0 +0.8 +0.6 +0.4 +0.2
+85C
+25C
-40C
+85C 10 12 14 16
06983-030
+125C 4 6 8 10 12 14 16
06983-033 06983-035
-VS
SUPPLY VOLTAGE (VS)
SUPPLY VOLTAGE (VS)
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 k
Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, RL = 10 k
25 20
10
+Vs
OUTPUT VOLTAGE SWING (V)
FAULT CONDITION (OVER-DRIVEN INPUT) 15 G=1000
FAULT CONDITION (OVER-DRIVEN INPUT) G=1000
15
+25C
+85C 10 -40C +125C 0 +85C +125C
+25C
CURRENT (mA)
5
5 0 -5 -10 -15 -20 -Vs +IN -IN +IN -IN
-5
-10
-100m
-100
06983-031
1k LOAD RESISTANCE ()
10k
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 31. Fault Current Draw vs. Input Voltage, G = 1000, RL = 10 k
Figure 34. Output Voltage Swing vs. Load Resistance
+VS -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 +85C +125C
+VS -0.4
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
-0.8 -1.2 -1.6 -2.0 +2.0 +1.6 +1.2 +0.8 +0.4
-40C +25C +85C +125C
+25C
-40C +85C
+1.2 +1.0 +0.8 +0.6 +0.4 +0.2 4 -VS
-40C
+25C
+125C
6
8
10
12
14
16
06983-032
-VS
4
6
8
10
12
14
16
SUPPLY VOLTAGE (VS)
OUTPUT CURRENT (mA)
Figure 32. Output Voltage Swing vs. Supply Voltage, G = 1000, RL = 2 k
Figure 35. Output Voltage Swing vs. Output Current
Rev. 0 | Page 12 of 24
06983-034
1m
1
-10
-1
-10/ 10
-1m
10m
-10m
100m
100
10
-25
-15 100
-40C
AD8253
5V/DIV
NO LOAD 47pF 100pF
1392ns TO 0.01% 1712ns TO 0.001% 0.002%/DIV
TIME (s)
Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1
Figure 39. Large-Signal Pulse Response and Settling Time, G = 100, RL = 10 k
5V/DIV
5V/DIV
664ns TO 0.01% 744ns TO 0.001% 0.002%/DIV
0.002%/DIV
12.88s TO 0.01% 16.64s TO 0.001%
06983-037
TIME (s)
TIME (s)
Figure 37. Large-Signal Pulse Response and Settling Time, G = 1, RL = 10 k
Figure 40. Large-Signal Pulse Response and Settling Time, G = 1000, RL = 10 k
5V/DIV
656ns TO 0.01% 840ns TO 0.001% 0.002%/DIV
TIME (s)
06983-038
2s/DIV
20mV/DIV
2s/DIV
Figure 38. Large-Signal Pulse Response and Settling Time, G = 10, RL = 10 k
Figure 41. Small-Signal Response, G = 1, RL = 2 k, CL = 100
Rev. 0 | Page 13 of 24
06983-041
06983-040
2s/DIV
10s/DIV
06983-039
20mV/DIV
2s/DIV
06983-036
2s/DIV
AD8253
1400 1200 1000 SETTLED TO 0.001%
TIME (ns)
800 600 SETTLED TO 0.01% 400 200 0
20mV/DIV
2s/DIV
06983-042
2
4
6
8
10
12
14
16
18
20
STEP SIZE (V)
Figure 42. Small-Signal Response, G = 10, RL = 2 k, CL = 100 pF
Figure 45. Settling Time vs. Step Size, G = 1, RL = 10 k
1400 1200 1000
TIME (ns)
SETTLED TO 0.001%
800 SETTLED TO 0.01% 600 400
20mV/DIV
20s/DIV
06983-043
200 0
2
4
6
8
10
12
14
16
18
20
STEP SIZE (V)
Figure 43. Small-Signal Response, G = 100, RL = 2 k, CL = 100 pF
Figure 46. Settling Time vs. Step Size, G = 10, RL = 10 k
2000 1800 1600 1400 SETTLED TO 0.01%
TIME (ns)
SETTLED TO 0.001%
1200 1000 800 600 400
06983-044
20mV/DIV
20s/DIV
200 2 4 6 8 10 12 14 16 18 20
06983-047
0
STEP SIZE (V)
Figure 44. Small-Signal Response, G = 1000, RL = 2 k, CL = 100 pF
Figure 47. Settling Time vs. Step Size, G = 100, RL = 10 k
Rev. 0 | Page 14 of 24
06983-046
06983-045
AD8253
20 18 16 14
THD + N (dB) 0
SETTLED TO 0.001%
-10 -20 -30 -40
TIME (s)
12 10 8 6 4 2
SETTLED TO 0.01%
-50 -60 -70 -80 -90
G = 1000 G = 100 G = 10
G=1
-100 -110
06983-048
2
4
6
8
10
12
14
16
18
20
100
1k
10k
100k
1M
STEP SIZE (V)
FREQUENCY (Hz)
Figure 48. Settling Time vs. Step Size, G = 1000, RL = 10 k
Figure 50. Total Harmonic Distortion vs. Frequency, 10 Hz to 500 kHz Band-Pass Filter, 2 k Load
0 -10 -20 -30 -40
THD + N (dB)
-50 -60 -70 -80 -90 G = 10 G=1 G = 1000 G = 100
-100 -110 100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 49. Total Harmonic Distortion vs. Frequency, 10 Hz to 22 kHz Band-Pass Filter, 2 k Load
06983-049
-120 10
Rev. 0 | Page 15 of 24
06983-050
0
-120 10
AD8253 THEORY OF OPERATION
+VS +VS A0 2.2k +VS -IN 1.2k A1 -VS +VS DIGITAL GAIN CONTROL 10k 10k -VS -VS A1
A3 -VS +VS
OUT
+VS 1.2k A2
10k
10k
REF
+IN
-VS WR
+VS 2.2k
+VS
-VS
DGND
06983-061
-VS
-VS
Figure 51. Simplified Schematic
The AD8253 is a monolithic instrumentation amplifier based on the classic 3-op-amp topology, as shown in Figure 51. It is fabricated on the Analog Devices, Inc., proprietary iCMOS(R) process that provides precision linear performance and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 10, 100, and 1000. Gain control is achieved by switching resistors in an internal precision resistor array (as shown in Figure 51). All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser-trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout optimized for high CMRR over frequency enables the AD8253 to offer a guaranteed minimum CMRR over frequency of 80 dB at 20 kHz (G = 1). The balanced input reduces the parasitics that in the past had adversely affected CMRR performance.
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 52 shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. Table 5 is the truth table for transparent gain mode, and Figure 52 shows the AD8253 configured in transparent gain mode.
+15V
10F
0.1F
WR A1 A0
-15V +5V +5V G = 1000
+IN
GAIN SELECTION
This section describes how to configure the AD8253 for basic operation. Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table (Table 2) for the permissible voltage range of DGND. The gain of the AD8253 can be set using two methods: transparent gain mode and latched gain mode. Regardless of the mode, pull-up or pull-down resistors should be used to provide a well-defined voltage at the A0 and A1 pins.
-IN
AD8253
REF
DGND 10F 0.1F
DGND
Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000
Rev. 0 | Page 16 of 24
06983-051
-15V NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO -VS. THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000.
AD8253
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR -VS -VS -VS -VS A1 Low Low High High A0 Low High Low High Gain 1 10 100 1000
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR High to Low High to Low High to Low High to Low Low to Low Low to High High to High
1
Latched Gain Mode
Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8253 can be set using WR as a latch, allowing other devices to share A0 and A1. Figure 53 shows a schematic using this method, known as latched gain mode. The AD8253 is in this mode when WR is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table listing in Table 6 for more on these gain changes.
+15V WR 10F 0.1F A1 A0 +IN WR A1 A0 +5V 0V +5V 0V +5V 0V G = 1000
A1 Low Low High High X1 X1 X1
A0 Low High Low High X1 X1 X1
Gain Change to 1 Change to 10 Change to 100 Change to 1000 No change No change No change
X = don't care.
On power-up, the AD8253 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8253 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 on power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for a minimum setup time, tSU, before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time, tHD, after the downward edge of WR to ensure that the gain is latched in correctly. After tHD, A0 and A1 may change logic levels, but the gain does not change until the next downward edge of WR. The minimum duration that WR can be held high is t WR-HIGH, and t WR-LOW is the minimum duration that WR can be held low. Digital timing specifications are listed in Table 2. The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in Figure 54. When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8253. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board.
+
G = PREVIOUS STATE REF
AD8253
-IN
-
DGND
DGND
10F
0.1F
Figure 53. Latched Gain Mode, G = 1000
tWR-HIGH
WR
06983-052
-15V NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000.
tWR-LOW
tSU
A0, A1
tHD
06983-053
Figure 54. Timing Diagram for Latched Gain Mode
Rev. 0 | Page 17 of 24
AD8253
POWER SUPPLY REGULATION AND BYPASSING
The AD8253 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier. Place a 0.1 F capacitor close to each supply pin. A 10 F tantalum capacitor can be used farther away from the part (see Figure 55) and, in most cases, it can be shared by other precision integrated circuits.
+VS 0.1F WR A1 A0 10F
INCORRECT
+VS
CORRECT
+VS
AD8253
REF
AD8253
REF
-VS TRANSFORMER +VS
-VS TRANSFORMER +VS
AD8253
REF
VOUT LOAD
AD8253
REF 10M
+IN
AD8253
-IN DGND 0.1F DGND -VS REF
-VS THERMOCOUPLE +VS
06983-054
-VS THERMOCOUPLE +VS C 1 fHIGH-PASS = 2RC REF R C R
06983-055
10F
C
Figure 55. Supply Decoupling, REF, and Output Referred to Ground
C
AD8253
AD8253
REF
INPUT BIAS CURRENT RETURN PATH
The AD8253 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 56).
-VS
-VS CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 56. Creating an IBIAS Path
INPUT PROTECTION
All terminals of the AD8253 are protected against ESD. An external resistor should be used in series with each of the inputs to limit current for voltages greater than 0.5 V beyond either supply rail. In such a case, the AD8253 safely handles a continuous 6 mA current at room temperature. For applications where the AD8253 encounters extreme overload voltages, external series resistors and low leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s should be used.
Rev. 0 | Page 18 of 24
AD8253
REFERENCE TERMINAL
The reference terminal, REF, is at one end of a 10 k resistor (see Figure 51). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8253 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS or -VS by more than 0.5 V. For best performance, especially in cases where the output is not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic resistance can adversely affect CMRR and gain accuracy.
INCORRECT CORRECT
Coupling Noise
To prevent coupling noise onto the AD8253, follow these guidelines: * * * Do not run digital lines under the device. Run the analog ground plane under the AD8253. Shield fast-switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. Avoid crossover of digital and analog signals. Connect digital and analog ground at one point only (typically under the ADC). Power supply lines should use large traces to ensure a low impedance path. Decoupling is necessary; follow the guidelines listed in the Power Supply Regulation and Bypassing section.
* * *
Common-Mode Rejection
The AD8253 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in amps whose CMRR falls off around 200 Hz. They often need common-mode filters at the inputs to compensate for this shortcoming. The AD8253 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering. Careful board layout maximizes system performance. To maintain high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input pins and traces. Source resistance and capacitance should be placed as close to the inputs as possible. Should a trace cross the inputs (from another layer), it should be routed perpendicular to the input traces.
AD8253
VREF VREF +
AD8253
OP1177
06983-056
-
Figure 57. Driving the Reference Pin
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8253 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8253 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 28 and Figure 29 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains.
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 58. The filter limits the input signal bandwidth according to the following relationship:
LAYOUT
Grounding
In mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8253 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board can cause an error. Therefore, use separate analog and digital ground planes. Only at one point, star ground, should analog and digital ground meet. The output voltage of the AD8253 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground.
FilterFreq DIFF = FilterFreq CM = where CD 10 CC.
1 2 R( 2C D + C C ) 1 2 RC C
Rev. 0 | Page 19 of 24
AD8253
+15V 0.1F CC R +IN CD R -IN CC 0.1F -15V 10F
06983-057
10F
AD8253
REF
VOUT
In this example, a 1 nF capacitor and a 49.9 resistor create an antialiasing filter for the AD7612. The 1 nF capacitor also serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 49.9 series resistor reduces the burden of the 1 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7612. Selecting too small a resistor improves the correlation between the voltage at the output of the AD8253 and the voltage at the input of the AD7612 but may destabilize the AD8253. A tradeoff must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability.
+15V
Figure 58. RFI Suppression
10F
0.1F WR A1 +12V A0 0.1F 0.1F -12V
Values of R and CC should be chosen to minimize RFI. Mismatch between the R x CC at the positive input and the R x CC at negative input degrades the CMRR of the AD8253. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved.
+IN
AD8253
REF -IN DGND 10F 0.1F
49.9 1nF
AD7612
+5V ADR435
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
An instrumentation amplifier is often used in front of an analogto-digital converter to provide CMRR. Usually, instrumentation amplifiers require a buffer to drive an ADC. However, the low output noise, low distortion, and low settle time of the AD8253 make it an excellent ADC driver.
DGND
06983-058
-15V
Figure 59. Driving an ADC
Rev. 0 | Page 20 of 24
AD8253 APPLICATIONS INFORMATION
DIFFERENTIAL OUTPUT
In certain applications, it is necessary to create a differential signal. High resolution analog-to-digital converters often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. Figure 61 shows how to configure the AD8253 to output a differential signal. An op amp, the AD8675, is used in an inverting topology to create a differential voltage. VREF sets the output midpoint according to the equation shown in the figure. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers. When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC.
+15V 0.1F AMPLITUDE +5V +IN WR A1 A0 AMPLITUDE VOUTA = VIN + VREF 2 REF 4.99k G=1 +2.5V 0V -2.5V
SETTING GAINS WITH A MICROCONTROLLER
+15V 10F 0.1F WR A1 +IN A0 MICROCONTROLLER
+
AD8253
-IN
-
DGND
REF
DGND
06983-059
10F
0.1F
-15V
Figure 60. Programming Gain Using a Microcontroller
-5V
+
VIN
AD8253
-
TIME
0.1F
DGND
-
-15V 4.99k +15V 10F -15V 10F DGND -15V 56pF 0.1F
+ AD8675 +15V
0.1F
VREF 0V AMPLITUDE +2.5V 0V -2.5V
VOUTB = -VIN + VREF 2
TIME
Figure 61. Differential Output with Level Shift
Rev. 0 | Page 21 of 24
06983-060
AD8253
DATA ACQUISITION
The AD8253 makes an excellent instrumentation amplifier for use in data acquisition systems. Its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit ADCs. Figure 63 shows the AD825x as part of a total data acquisition system. The quick slew rate of the AD8253 allows it to condition rapidly changing signals from the multiplexed inputs. An FPGA controls the AD7612, AD8253, and ADG1209. In addition, mechanical switches and jumpers allow users to pin strap the gains when in transparent gain mode. This system achieved -116 dB of THD at 1 kHz and a signal-tonoise ratio of 91 dB during testing, as shown in Figure 62.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170
AMPLITUDE (dB)
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (kHz)
Figure 62. FFT of the AD825x in a Total Data Acquisition System Using the AD8253 1 kHz Signal
JMP JMP +5V 2k
+12V 0.1F
14
+12V + 10F
+
-12V
-VS
10F
GND
2
+CH1 +CH2 +CH3 +CH4 -CH4 -CH3 -CH2 -CH1
806 806 806 806 806 806 806 806
VDD
4 S1A 5 S2A 6 S3A 7 S4A
EN DGND
DGND
JMP +5V 2k WR
5
DGND
2
DGND 6 DA 8 0 0 CD
CC
ALTERA EPF6010ATC144-3
CC +IN
10
ADG1209
10 S4B 11 S3B 12 S2B
13
+
DB 9 GND 15 A0
1
0
0
-IN
A1 4 A0 AD8253 REF +VS
8
DGND
7
VOUT 0 49.9
+IN 1nF
AD7612
1
-
-VS
3
9
ADR435 C4 0.1F
S1B A1 VSS 16
3
C3 0.1F +12V -12V JMP +5V 2k
0.1F -12V
DGND JMP +5V R8 2k
06983-067
DGND
Figure 63. Schematic of ADG1209, AD8253, and AD7612 Used with the AD825x in a Total Data Acquisition System
Rev. 0 | Page 22 of 24
06983-062
AD8253 OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
Figure 64. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8253ARMZ 1 AD8253ARMZ-RL1 AD8253ARMZ-R71 AD8253-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board
Package Option RM-10 RM-10 RM-10
Branding X X X
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
AD8253 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06983-0-7/08(0)
Rev. 0 | Page 24 of 24

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